1 white electronic designs corporation ? phoenix, az ? (602) 437-1520 hi-reliability product 512kx16 cmos eeprom module WE512K16-XG4X features n access time of 140, 150, 200ns n packaging: ? 68 lead, 40mm hermetic cqfp (package 501) n organized as 4 banks of 128kx16 n write endurance 10,000 cycles n data retention ten years minimum n military temperature range n low power cmos n automatic page write operation n page write cycle time: 10ms max n data polling for end of write detection n hardware and software data protection n ttl compatible inputs and outputs n 5 volt power supply n 8 built-in decoupling caps and multiple ground pins for low noise operation n weight - 20 grams typical april 1999 rev. 2 fig. 1 pin configuration 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc a 11 a 12 a 13 a 14 a 15 a 16 cs 2 oe cs 4 nc nc nc nc nc nc nc nc nc inc nc nc nc nc nc gnd nc nc nc nc nc nc nc nc nc a 0 a 1 a 2 a 3 a 4 a 5 cs 1 gn d cs 3 we a 6 a 7 a 8 a 9 a 10 v cc pin description block diagram top view 128k x 8 i/o 0-7 cs 1 128k x 8 i/o 8-15 cs 2 cs 3 128k x 8 128k x 8 cs 4 a 0-16 oe we 128k x 8 128k x 8 128k x 8 128k x 8 i/o 0-15 data inputs/outputs a 0-16 address inputs we write enable cs 1-4 chip selects oe output enable v cc power supply gnd ground nc not connected note: cs 1-4 are used as bank selects. during reads, only one csx can be active at one time.
2 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WE512K16-XG4X absolute maximum ratings truth table fig. 2 ac test circuit ac test conditions i current source d.u.t. c = 50 pf eff i ol v 1.5v (bipolar supply) z current source oh notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z 0 = 75 w . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. recommended operating conditions dc characteristics (v cc = 5.0v, gnd = 0v, t a = -55 c to +125 c) parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v parameter symbol unit operating temperature t a -55 to +125 c storage temperature t stg -65 to +150 c signal voltage relative to gnd v g -0.6 to +6.25 v voltage on oe and a9 -0.6 to +13.5 v note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. cs oe we mode data i/o h x x standby high z l l h read data out l h l write data in x h x out disable high z/data out x x h write x l x inhibit parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.0 vcc + 0.3 v input low voltage v il -0.3 +0.8 v operating temp. (mil.) t a -55 +125 c parameter symbol conditions min max unit input leakage current i li v cc = 5.5, v in = gnd to v cc 10 m a output leakage current i lo cs = v ih , oe = v ih , v out = gnd to v cc 10 m a operating supply current (x16) i ccx16 cs 1 = v il , oe = cs 2-4 = v ih , f = 5mhz, v cc = 5.5 160 ma chip erase current i cc1 cs = v il , oe = v ih , f = 5mhz, v cc = 5.5 250 ma standby current (cmos) i sb cs = v ih , oe = v ih , f = 5mhz, v cc = 5.5 5 ma output low voltage v ol i ol = 2.1ma, v cc = 4.5v 0.45 v output high voltage v oh i oh = -400 m a, v cc = 4.5v 2.4 v note: dc test conditions: v ih = v cc -0.3v, v il = 0.3v capacitance (t a = +25 c) parameter symbol conditions max unit oe capacitance c oe v in = 0 v, f = 1.0 mhz 50 pf we capacitance c we v in = 0 v, f = 1.0 mhz 50 pf cs 1-4 capacitance c cs v in = 0 v, f = 1.0 mhz 25 pf data i/o capacitance c i/o v i/o = 0 v, f = 1.0 mhz 40 pf address input capacitance c ad v in = 0 v, f = 1.0 mhz 70 pf this parameter is guaranteed by design but not tested.
3 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WE512K16-XG4X write a write cycle is initiated when oe is high and a low pulse is on we or cs with cs or we low. the address is latched on the falling edge of cs or we whichever occurs last. the data is latched by the rising edge of cs or we, whichever occurs first. a word write operation will automatically continue to completion. write cycle timing figures 3 and 4 show the write cycle timing relationships. a write cycle begins with address application, write enable and chip select. chip select is accomplished by placing the cs line low. write enable consists of setting the we line low. the write cycle begins when the last of either cs or we goes low. the we line transition from high to low also initiates an internal 150 m sec delay timer to permit page mode operation. each subsequent we transition from high to low that occurs before the completion of the 150 m sec time out will restart the timer from zero. the operation of the timer is the same as a retriggerable one-shot. ac write characteristics (v cc = 5.0v, gnd = 0v, t a = -55 c to +125 c) write cycle parameter symbol min max unit write cycle time, typ = 6ms t wc 10 ms address set-up time t as 10 ns write pulse width (we or cs) t wp 120 ns chip select set-up time t cs 0ns address hold time t ah 100 ns data hold time t dh 10 ns chip select hold time t csh 0ns data set-up time t ds 100 ns output enable set-up time t oes 10 ns output enable hold time t oeh 10 ns write pulse width high t wph 50 ns
4 white electronic designs corporation ? phoenix, az ? (602) 437-1520 fig. 3 write waveform we controlled fig. 4 write waveform cs controlled t address cs 1-4 we data in dh t wph t wp t csh t oeh t ah t oes t as t cs oe t wc t ds t address we cs 1 - 4 data in dh t wph t wp t csh t oeh t ah t oes t as t cs oe t ds t wc WE512K16-XG4X
5 white electronic designs corporation ? phoenix, az ? (602) 437-1520 ac read characteristics (v cc = 5.0v, gnd = 0v, t a = -55 c to +125 c) fig. 5 read waveform t address cs 1-4 oe output oh t df t acc t rc t oe t acs output valid address valid high z read the module stores data at the memory location determined by the address pins. when cs and oe are low and we is high, this data is present on the outputs. when cs and oe are high, the outputs are in a high impedance state. this two line control prevents bus contention. notes: oe may be delayed up to t acs - t oe after the falling edge of cs without impact on t oe or by t acc - t oe after an address change without impact on t acc . cs 1-4 are used as bank selects. during reads, only one csx can be active at one time. read cycle parameter symbol -140 -150 -200 unit min max min max min max read cycle time t rc 140 150 200 ns address access time t acc 140 150 200 ns chip select access time t acs 140 150 200 ns output hold from add. change, oe or cs t oh 000ns output enable to output valid t oe 050055055ns chip select or oe to high z output t df 50 70 70 ns WE512K16-XG4X
6 white electronic designs corporation ? phoenix, az ? (602) 437-1520 data polling the module offers a data polling feature which allows a faster method of writing to the device. figure 6 shows the timing diagram for this function. during a word or page write cycle, an attempted read of the last word written will result in the complement of the written data on i/o 7 and i/o 15 . once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the write cycle. data polling characteristics (v cc = 5.0v, gnd = 0v, t a = -55 c to +125 c) fig. 6 data polling waveform parameter symbol min max unit data hold time t dh 10 ns oe hold time t oeh 10 ns oe to output valid t oe 55 ns write recovery time t wr 0ns we t oeh t dh t oe t wr high z cs 1-4 oe i/o 7 i/o 15 address WE512K16-XG4X
7 white electronic designs corporation ? phoenix, az ? (602) 437-1520 page write operation the module has a page write operation that allows one to 128 words of data to be written into the device and consecutively loads during the internal programming period. successive words may be loaded in the same manner after the first data word has been loaded. an internal timer begins a time out operation at each write cycle. if another write cycle is completed within 150 m s or less, a new time out period begins. each write cycle restarts the delay period. the write cycles can be continued as long as the interval is less than the time out period. the usual procedure is to increment the least significant address lines from a 0 through a 6 at each write cycle. in this manner a page of up to 128 words can be loaded in to the eeprom in a burst mode before beginning the relatively long interval programming cycle. after the 150 m s time out is completed, the eeprom begins an internal write cycle. during this cycle the entire page of words will be written at the same time. the internal programming cycle is the same regardless of the number of words accessed. page write characteristics (v cc = 5.0v, gnd = 0v, t a = -55 c to +125 c) fig. 7 page mode write waveform 1. page address must remain valid for duration of write cycle. page mode write characteristics symbol unit parameter min max write cycle time, typ = 6ms t wc 10 ms address set-up time t as 0ns address hold time (1) t ah 50 ns data set-up time t ds 50 ns data hold time t dh 0ns write pulse width t wp 100 ns word load cycle time t blc 150 m s write pulse width high t wph 50 ns oe word 1 word 2 word 3 word 126 word 0 valid address t wc t blc t wph t wp address data cs 1-4 we word 127 t ds t dh t as t ah WE512K16-XG4X
8 white electronic designs corporation ? phoenix, az ? (602) 437-1520 load data aaaa to address 5555 load data 5555 to address 2aaa load data a0a0 to address 5555 load data xxxx to any address (4) load last word to last address fig. 8 software data protection enable algorithm (1) t t t t writes enabled (2) notes: 1. data format: i/o 15 - 0 (hex); address format: a 16 - 0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 words of data may be loaded. enter data protect state WE512K16-XG4X
9 white electronic designs corporation ? phoenix, az ? (602) 437-1520 hardware data protection these features protect against inadvertent writes to the module. these are included to improve reliability during normal operation: a) v cc power on delay as v cc climbs past 3.8v typical the device will wait 5 msec typical before allowing write cycles. b) v cc sense while below 3.8v typical write cycles are inhibited. c) write inhibiting holding oe low and either cs or we high inhibits write cycles. d) noise filter pulses of <8ns (typ) on we or cs will not initiate a write cycle. software data protection a software write protection feature may be enabled or disabled by the user. when shipped by white microelectronics, the module has the feature disabled. write access to the device is unrestricted. to enable software write protection, the user writes three access code words to three special internal locations. once write protection has been enabled, each write to the eeprom must use the same three-word write sequence to permit writing. after setting software data protection, any attempt to write to the device without the three-word command sequence will start the internal write timers. no data will be written to the device, however, for the duration of t wc . the write protection feature can be disabled by a six-word write sequence of specific data to specific locations. power transitions will not reset the software write protection. each 128k-word block of the eeprom has independent write protection. one or more blocks may be enabled and the rest disabled in any combination. the software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a prom programmer. fig. 9 software data protection disable algorithm (1) t t t t t t t exit data protect state notes: 1. data format: i/o 15 - 0 (hex); address format: a 16 - 0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 words of data may be loaded. (3) load data aaaa to address 5555 load data 5555 to address 2aaa load data 8080 to address 5555 load data aaaa to address 5555 load data 5555 to address 2aaa load data 2020 to address 5555 load data xxxx to any address (4) load last word to last address WE512K16-XG4X
10 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WE512K16-XG4X package 501: 68 lead, ceramic quad flat pack, cqfp (g4) all linear dimensions are millimeters and parenthetically in inches 0.38 (0.015) 0.08 (0.003) 68 places 1.27 (0.050) typ 5.1 (0.200) max 39.6 (1.56) 0.38 (0.015) sq 38 (1.50) typ 4 places 5.1 (0.200) 0.25 (0.010) 4 places 12.7 (0.500) 0.5 (0.020) 4 places 0.25 (0.010) 0.05 (0.002) 1.27 (0.050) 0.1 (0.005) pin 1 identifier pin 1 ordering information lead finish: blank = gold plated leads a = solder dip leads processing: q = mil-std-883 compliant m = military screened -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c package: g4 = 40mm ceramic quad flat pack, cqfp (package 501) access time (ns) organization, 4 banks of 128kx16 eeprom white electronic designs corp. w e 512k16 - xxx g4 x x
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